Multiprocessor System on Chip
2010 Addendum
An on-chip multiprocessor, with multiple cores on the same die, is now
simply referred to as a
chip multiprocessor
(CMP).
Multicore Processors and Systems
(Keckler, Olukotun and Hofstee, editors)
The Preface
(download here)
of this book provides an overview of CMP hardware,
from homogeneous “bulldozers”, to ALU arrays (GPU “termites”),
with “chainsaws” in between.
Velox Project
|
AMD ASF Proposal
High level memory fence programming, referred to as
transactions.
|
|
“If, when a
transaction finishes, none of its transactional lines
have been invalidated or evicted, then it can commit”
|
|
—
|
Herlihy & Shavit,
The Art of Multi-
processor Programming,
p. 447
|
|
|
|
“Before resuming from an interrupt, the STM runtime resets
all mark bits.
This does not abort the pending transaction – it merely causes a
full software validation on commit.”
|
|
—
|
Adl-Tabatabai, Kozyrakis, & Saha,
“Optimizing Memory Transactions for
Multicore Systems”, in Keckler et.al.
|
|
|
|
